The present invention relates to a semiconductor integrated circuit device having a plurality of clock driver circuits dispersedly arranged in a core region in a semiconductor integrated circuit, the clock driver circuits supplying appropriate clock signals to a plurality of cells using the clock signals and arranged in the core region, through clock signal supply lines interconnected in a mesh in the core region, and a method of trying out the clock driver circuits.
Conventionally, in a semiconductor integrated circuit device such as an ECA (Embedded Cell Array) or a cell base, the interior region (core region) has two kinds of cells therein. That is, a plurality of cells acting as logic circuits, such as AND or OR circuits, and a plurality of cells acting as a flip-flop circuit or a memory circuit, each requiring clock signals, wherein a clock driver circuit is provided for supplying the clock signals to the cells such as the flip-flop circuit or the memory circuit.
FIG. 8 shows a constitution of a conventional semiconductor integrated circuit device. The semiconductor integrated circuit device 100 has a core region 101 (internal integrated circuit group) and a buffer region 102 (peripheral circuit region). A first signal driver circuit 103 (input driver) is located in the central portion of one side of the core region 101 to amplify a clock signal produced from outside of the semiconductor integrated circuit device 100. A plurality of second signal driver circuits 104 (104a-1 to 104a-4, 104b-1 to 104b-4, 104c-1 to 104c-4, 104d-1 to 104d-4) (main driver) are uniformly located in the core region 101 vertically and horizontally.
Third signal driver circuits 105a, 105b and fourth signal driver circuits 106a-106d (predrivers) are uniformly located between the first signal driver circuit 103 and the second signal driver circuits 104. A clock signal output by the first driver circuit 103 is supplied to the respective second signal driver circuits 104 in an even manner. A signal line 107 interconnects the first signal driver circuit 103 to the third driver circuits 105a, 105b. Further, signal line 108a interconnects the third signal driver circuit 105a to the fourth signal driver circuits 106a, 106b. The signal line 108b interconnects the third signal driver circuit 105b to the fourth driver circuits 106c, 106d. Further, signal lines 109a-109d interconnect the fourth signal driver circuits 106a-106d to each of the first signal driver circuits 104, respectively.
Clock signal supply lines 110-1 to 110-n belong to an interconnection line group consisting of lines arranged vertically in the core region 101. Clock signal supply lines 111-1 to 111-n belong to an interconnection line group consisting of lines arranged horizontally in the core region 101. The clock signal supply lines 110-1 to 110-n and the clock signal supply lines 111-1 to 111-n are connected in a cross relation to each other to form a mesh-like interconnection pattern. The second signal driver circuits 104 as mentioned above are uniformly located and connected to the mesh-like lines formed by the clock signal supply lines 110-1 to 110-n, 111-1 to 111-n. The clock signals supplied to the mesh-like interconnection lines are supplied to megacells 301a, 301b and flip-flop circuit cell groups 302, each requiring the clock signals in the core region 101.
Clock signals are supplied to the semiconductor integrated circuit device 100, and the clock signals output by the first signal driver circuit 103 are uniformly supplied to the second signal driver circuits 104 with the third signal driver circuits 105a, 105b and the fourth signal driver circuits 106a-106d symmetrically arranged to each other between the first signal driver circuit 103 and the second signal driver circuits 104, whereby the clock signals are uniformly supplied to the mesh-like clock signal supply lines 110-1 to 110-n and 111-1 to 111-n. This allows unevenness of the clock signals reaching the megacells 301a, 301b and the flip-flop circuit cell groups 302 in the core region 101 to be reduced, resulting in a variety of signal processes using clock signals with reduced clock skews in the internal integrated circuit groups in the core region 101.
In modern technology of semiconductor integrated circuit devices, however, there is always an increasing need for high-speed operations, and accordingly, semiconductor integrated circuit devices having clock driver circuits with considerably reduced clock skews are required. There are several problems with the above mentioned conventional semiconductor integrated circuit device, which may cause an inability to meet there requirements.
For example, as shown in FIG. 8, when the megacells 301a, 301b are unevenly arranged in the core region 101, or the flip-flop circuit cell groups 302 are densely or sparsely arranged therein, the signal supply load on each of the second signal driver circuits 104 widely vary for the megacells 301a, 301b and the flip-flop circuit cell groups 302. For this reason, the clock skews maybe increased for high-speed clock signals, even when the mesh-like interconnected clock signal supply lines 110-1 to 110-n and 111-1 to 111-n are used as shown in FIG. 8.
In this case, it can be a solution to reduce the clock skews that the megacells 301a, 301b and the flip-flop circuit cell groups 302 each requiring clock signals are re-arranged to provide a uniform signal supply load in the core region 101. However, this re-arrangement requires considerable time and labor for the layout and raises a problem of the delayed development of semiconductor integrated circuit devices.
It is an object of the present invention to provide a semiconductor integrated circuit device and a layout method of a clock driver considerably reducing clock skews without requiring the re-arrangement of cells in the core region 101, other than the clock driver circuit.
According to the semiconductor integrated circuit device of one aspect of the present invention an adjustment is carried out such that the plurality of clock driver circuits are arranged by increasing or decreasing the number of rows of transistors in each of the clock driver circuits based on the density of the cells using the clock signals in the neighboring regions of each of the dispersedly arranged clock driver circuits, by using MOS transistors of MOS transistor groups arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which the core region is divided.
According to the semiconductor integrated circuit device of another aspect of the present invention, an adjustment is carried out such that the plurality of clock driver circuits are arranged by increasing or decreasing the number of clock driver circuits in the neighboring regions based on the density of the cells using the clock signals in the neighboring regions of each of the dispersedly arranged clock driver circuits, by using MOS transistors of MOS transistor groups arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which the core region is divided.
According to the semiconductor integrated circuit device of still another aspect of the present invention, an adjustment is carried out such that the plurality of clock driver circuits are arranged by shifting each of the clock driver circuits based on the density of the cells using the clock signals in the neighboring regions of each of the dispersedly arranged clock driver circuits, by using MOS transistors of MOS transistor groups arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which the core region is divided.
According to the semiconductor integrated circuit device of still another aspect of the present invention, an adjustment is carried out such that the plurality of clock driver circuits are arranged by making a combination of increasing or decreasing the number of rows of transistors in each of the clock driver circuits, increasing or decreasing the number of clock driver circuits, and/or shifting each of the clock driver circuits based on the density of the cells using the clock signals in the neighboring regions of each of the dispersedly arranged clock driver circuits, by using MOS transistors of MOS transistor groups arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which the core region is divided.
According to the layout method of still another aspect of the present invention, an adjustment is carried out such that in the arrangement step MOS transistors of MOS transistor groups are arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which the core region is divided, in the layout step a layout process for cells in the divided regions is processed, and in the number controlling step the number of rows of transistors in each of the clock driver circuits is increased or decreased based on the density of the cells using the clock signals in the neighboring regions of each of the dispersedly arranged clock driver circuits, by using the MOS transistors of the MOS transistor groups in an array in the arrangement step.
According to the layout method of still another aspect of the present invention, an arrangement is carried out such that in the arrangement step MOS transistors of MOS transistor groups are arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which the core region is divided, in the layout step a layout process for cells in the divided regions is processed, and in the number controlling step the number of clock driver circuits in the neighboring regions is increased or decreased based on the density of the cells using the clock signals in the neighboring regions of each of the dispersedly arranged clock driver circuits, by using the MOS transistors of the MOS transistor groups in an array in the arrangement step.
According to the layout method of still another aspect of the present invention, an arrangement is carried out such that in the arrangement step MOS transistors of MOS transistor groups are arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which the core region is divided, in the layout step a layout process for cells in the divided regions is processed, and in the sifting step each of the clock driver circuits is shifted based on the density of the cells using the clock signals in the neighboring regions of each of the dispersedly arranged clock driver circuits, by using the MOS transistors of the MOS transistor groups in an array in the arrangement step.
According to the layout method of still another aspect of the present invention, an arrangement is carried out such that in the arrangement step MOS transistors of MOS transistor groups are arranged in an array in the peripheral region and bounded region portions in a plurality of divided regions into which the core region is divided, in the layout step a layout process for cells in the divided regions is processed, and in the circuit arranging step a combination of increasing or decreasing the number of rows of transistors in each of the clock driver circuits, increasing or decreasing the number of clock driver circuits, and/or shifting each of the clock driver circuits is made based on the density of the cells using the clock signals in the neighboring regions of each of the dispersedly arranged clock driver circuits, by using the MOS transistors of the MOS transistor groups in an array in the arrangement step.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.